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| DATA SHEET MOS Integrated Circuit PD70732 V810TM 32-BIT MICROPROCESSOR The PD70732 (a.k.a. V810) microprocessor is NEC's first microprocessor of the V810 family TM for embedded control applications. The V810 employs a RISC architecture for embedded control applications. This product has high-speed real time response, high-speed integer operation instruction, bit string instruction, floating-point operation instruction, and significantly high cost performance is realized for applications such as facsimile, digital PPC, word processor, image processor, real time control device, etc. The functions are described in detail in the following User's Manuals, which should be read before starting design work. * V805TM, V810 User's Manual Hardware : U10661E * V810 Family User's Manual Architecture : U10082E Features High-performance 32-bit architecture for embedded control application * 32-bit separate address/data bus * 1-Kbyte cache memory * * * * Pipeline structure of 1 clock pitch 16-bit fixed instructions (with some exceptions) 32-bit general-purpose registers: 32 4-Gbyte linear address space * Register/flag hazard interlocked by hardware Dynamic bus sizing function (16 bits) 16-bit bus fixing function 16-bit bus system can be configured. Instructions ideal for various application fields * Floating-point operation instructions (based upon IEEE754 data format) * Bit string instructions 16 levels of high-speed interrupt responses Clock can be stopped by internal static operation Maximum operating frequency: 16/20/25 MHz Low voltage: VDD = 2.7 to 3.6 V (Max. 16 MHz) VDD = 2.2 to 3.6 V (Max. 10 MHz) Small package versions available (14 x 14 mm fine-pitch TQFP) 5 The information in this document is subject to change without notice. The mark 5 shows major revised points. Document No. U10691EJ3V0DS00 (3rd edition) Date Published September 1996 P Printed in Japan (c) 1993 PD70732 Ordering Information Part Number Package 120-pin plastic QFP (28 x 28 mm) 120-pin plastic QFP (28 x 28 mm) 120-pin plastic QFP (28 x 28 mm) 120-pin plastic TQFP (Fine pitch) (14 x 14 mm) 176-pin ceramic PGA (Seam weld) Max. operating freq. (MHz) 16 20 25 25 25 PD70732GD-16-LBB PD70732GD-20-LBB PD70732GD-25-LBB 5 PD70732GC-25-9EV PD70732R-25 Pin Outline A31 to A1 V810 CLK D31 to D0 BE3 to BE0 RESET ST1, ST0 INT DA INTV3 to INTV0 MRQ R/W NMI HLDRQ BCYST HLDAK BLOCK READY SZRQ SIZ16B ICHEEN ADRSERR 2 PD70732 Pin Configuration * 120-pin plastic QFP (28 x 28 mm) (Top View) PD70732GD-xx-LBB VDD IC1 IC1 IC1 RESET D0 D1 D2 GND D3 D4 GND D5 D6 D7 VDD VDD D8 D9 D10 D11 D12 GND D13 D14 D15 D16 D17 D18 GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 IC1 IC2 IC2 ICHEEN NMI INT INTV0 INTV1 INTV2 INTV3 BLOCK GND VDD CLK GND SIZ16B DA VDD BCYST HLDAK ADRSERR BE0 BE1 A1 BE2 BE3 R/W MRQ ST1 GND 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 VDD ST0 HLDRQ SZRQ READY A2 A3 A4 A5 A6 A7 A8 GND A9 VDD VDD GND A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 GND Cautions 1. Leave the IC1 pin open. 2. Connect the IC2 pin to GND. Remark IC: Internally Connected VDD D19 D20 D21 GND D22 D23 D24 D25 D26 D27 D28 D29 D30 VDD GND VDD D31 A31 A30 A29 A28 A27 A26 A25 A24 A23 GND A22 VDD 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 3 PD70732 5 * 120-pin plastic TQFP (Fine pitch) (14 x 14 mm) (Top View) PD70732GC-25-9EV VDD D19 D20 D21 GND D22 D23 D24 D25 D26 D27 D28 D29 D30 VDD GND VDD D31 A31 A30 A29 A28 A27 A26 A25 A24 A23 GND A22 VDD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 GND D18 D17 D16 D15 D14 D13 GND D12 D11 D10 D9 D8 VDD VDD D7 D6 D5 GND D4 D3 GND D2 D1 D0 RESET IC1 IC1 IC1 VDD 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 IC1 IC2 IC2 ICHEEN NMI INT INTV0 INTV1 INTV2 INTV3 BLOCK GND VDD CLK GND SIZ16B DA VDD BCYST HLDAK ADRSERR BE0 BE1 A1 BE2 BE3 R/W MRQ ST1 GND Cautions 1. VDD is power supply pin. All VDD pins should be connected to a +5V power supply (the same power supply). 2. GND is ground pin. All GND pins should be connected to the same GND. 3. Leave the IC1 pin open. 4. Connect the IC2 pin to GND. Remark IC: Internally Connected 4 GND A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 GND VDD VDD A9 GND A8 A7 A6 A5 A4 A3 A2 READY SZRQ HLDRQ ST0 VDD 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 PD70732 * 176-pin ceramic PGA (Seam weld) PD70732R-25 Bottom View 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 QPNMLKJHGFEDCB A AB CDEFGHJKLMN P Q No. 1 pin index Top View Insertion guide pin Remark The insertion guide pin is not included in the number of pins. No. A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 B1 B2 Signal IC2 D12 D13 D10 GND D6 IC2 D5 IC2 D1 VDD RESET IC1 IC1 IC2 D17 D18 No. B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 C1 C2 C3 C4 Signal GND D11 GND D7 VDD D3 GND D0 GND IC1 GND IC1 ICHEEN VDD VDD D16 D14 No. C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 D1 D2 D3 D4 D5 D6 Signal VDD D8 VDD D4 D2 IC3 VDD IC1 IC2 VDD NMI D23 D22 D20 GND D15 D9 No. D7 D8 D9 D10 D11 D12 D13 D14 D15 E1 E2 E3 E4 E12 E13 E14 E15 Signal VDD VDD GND IC3 IC2 GND INT INTV1 GND D27 D25 D21 D19 IC3 INTV0 IC3 IC1 5 PD70732 No. F1 F2 F3 F4 F12 F13 F14 F15 G1 G2 G3 G4 G12 G13 G14 G15 H1 H2 H3 H4 H12 H13 H14 H15 J1 J2 J3 Signal VDD D26 D24 GND INTV2 INTV3 VDD GND D29 D28 IC2 IC2 VDD IC2 IC1 IC1 A31 D30 GND D31 GND CLK IC1 IC2 A30 A29 IC2 No. J4 J12 J13 J14 J15 K1 K2 K3 K4 K12 K13 K14 K15 L1 L2 L3 L4 L12 L13 L14 L15 M1 M2 M3 M4 M5 M6 Signal VDD IC2 IC2 IC1 IC1 IC2 A27 A25 A24 GND BLOCK VDD VDD A28 A26 A22 A20 HLDAK VDD IC1 IC1 GND A23 A21 GND A16 A10 No. M7 M8 M9 M10 M11 M12 M13 M14 M15 N1 N2 N3 N4 N5 N6 N7 N8 N9 N10 N11 N12 N13 N14 N15 P1 P2 P3 Signal VDD A5 VDD ST1 A1 GND BCYST DA SIZ16B VDD VDD A17 A15 VDD A9 VDD VDD A3 HLDRQ VDD BE2 BE1 VDD IC1 A18 A19 GND No. P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 Q9 Q10 Q11 Q12 Q13 Q14 Q15 Signal A12 GND A8 GND A6 GND SZRQ GND MRQ GND ADRSERR BE0 IC2 A13 A14 A11 GND A7 IC2 A4 IC2 A2 READY ST0 BE3 R/W IC2 Cautions 1. Leave the IC1 pin open. 2. Connect the IC2 pin to GND. 3. Connect the IC3 pin to power supply. Remark IC: Internally Connected 6 PD70732 CONTENTS 1. PIN FUNCTIONS .............................................................................................................................. 8 1.1 Pin Function List ................................................................................................................... 8 1.2 Pin I/O Circuits and Recommended Connection of Unused Pins ................................. 10 2. REGISTER SET ............................................................................................................................... 12 2.1 Program Register Set ........................................................................................................... 13 2.2 System Register Set ............................................................................................................. 14 3. DATA TYPES ................................................................................................................................... 15 3.1 Data Types ............................................................................................................................. 15 3.1.1 3.1.2 3.1.3 3.1.4 3.1.5 Data type and addressing ......................................................................................................... Integer ........................................................................................................................................ Unsigned integer ....................................................................................................................... Bit string ..................................................................................................................................... Single-precision floating-point data .......................................................................................... 15 16 16 16 17 5 5 5 3.2 Data Alignment ...................................................................................................................... 17 5 5 5 5 5 5 4. ADDRESS SPACE ........................................................................................................................... 18 5. BUS INTERFACE FUNCTION ......................................................................................................... 21 6. INTERRUPT AND EXCEPTION ....................................................................................................... 22 7. CACHE ............................................................................................................................................. 23 8. RESET .............................................................................................................................................. 24 9. INSTRUCTION SET ......................................................................................................................... 25 9.1 Instruction Format ................................................................................................................ 25 9.2 Instruction Mnemonic (in alphabetical order) ................................................................... 27 10. ELECTRICAL SPECIFICATIONS .................................................................................................... 10.1 Specifications When VDD = +5 V 10% .............................................................................. 10.2 Specifications When VDD = 2.7 to 3.6 V ............................................................................. 10.3 Specifications When VDD = 2.2 to 3.6 V ............................................................................. 37 38 47 51 11. PACKAGE DRAWINGS ................................................................................................................... 59 12. RECOMMENDED SOLDERING CONDITIONS ............................................................................... 62 7 PD70732 1. PIN FUNCTIONS 1.1 Pin Function List Bus hold status Name I/O Function during operation Hi-Z Bus hold status at reset Bus idle status at reset A31 to A1 (Address Bus) D31 to D0 (Data Bus) BE3 to BE0 (Byte Enable) ST1, ST0 (Status) DA (Data Access) MRQ (Memory Request) R/W (Read/Write) BCYST (Bus Cycle Start) READY (Ready) HLDRQ (Hold Request) HLDAK (Hold Acknowledge) SZRQ (Bus Sizing Request) SIZ16B (Bus Size 16 Bit) BLOCK (Bus Lock) ICHEEN (Instruction Cache Enable) INT (Maskable Interrupt) INTV3 to INTV0 (Interrupt Level) 3-state output 3-state I/O 3-state output 3-state output 3-state output 3-state output 3-state output 3-state output Input Address bus Hi-Z H Note Bidirectional data bus Hi-Z Hi-Z Hi-Z Indicates valid data bus when data is accessed Hi-Z Hi-Z H Indicates type of bus cycle Hi-Z Hi-Z H Strobe signal for bus cycle Hi-Z Hi-Z H Indicates memory access Hi-Z Hi-Z H Distinguishes between read access and write access Hi-Z Hi-Z H Indicates start of bus cycle Hi-Z Hi-Z H Extends bus cycle -- -- -- Input Requests bus mastership -- -- -- Output Acknowledges HLDRQ L L H Input Requests bus sizing -- -- -- Input Fixes external data bus width to 16 bits -- -- -- Output Requests to inhibit use of bus L L L Input Operates instruction cache -- -- -- Input Interrupt request -- -- -- Input Interrupt level -- -- -- Note A1 pin is "H" in the 16-bit bus fixed mode; otherwise, it is "L". 8 PD70732 Bus hold Bus hold status status during at reset operation -- -- Bus idle status at reset Name I/O Function NMI (Non-Maskable Interrupt) CLK RESET (Reset) ADRSERR (Address Error) VDD (Power Supply) GND (Ground) IC1 (Internally Connected 1) IC2 (Internally Connected 2) IC3 (Internally Connected 3) Input Non-maskable interrupt request -- Input Input CPU clock input Resets internal status -- -- -- -- -- -- Output Indicates that data alignment is illegal Not affected H H -- Positive power supply -- -- -- -- Ground potential (0 V) -- -- -- -- Internally connected (Leave this pin open.) -- -- -- -- Internally connected (Ground this pin.) -- -- -- -- Internally connected (Connect this pin to power supply.) -- -- -- 9 PD70732 5 1.2 Pin I/O Circuits and Recommended Connection of Unused Pins The I/O circuit type of each pin and recommended connection of unused pins are shown in Table 1-1. Figure 1-1 shows the I/O circuit of each type. Table 1-1. Pin I/O Circuit Types and Recommended Connection Method of Unused Pins Pin D31 to D0 A31 to A1 BE3 to BE0 ST1, ST0 DA MRQ R/W BCYST READY HLDRQ HLDAK SZRQ SIZ16B BLOCK ICHEEN INT INTV3 to INTV0 NMI CLK RESET ADRSERR IC1 IC2 IC3 4 -- -- -- Connect to GND Connect to VDD Open -- 4 1 4 1 1 Connect to GND via resistor Connect to VDD via resistor Open Connect to VDD via resistor Connect to GND via resistor Open Connect to VDD via resistor Connect to GND via resistor Connect to VDD via resistor I/O Circuit Type 5 4 Open Recommended Connection Method 10 PD70732 Figure 1-1. Pin I/O Circuit Type 1 VDD P-ch IN N-ch Type 5 VDD data P-ch IN/OUT output disable N-ch input enable Type 4 VDD data P-ch OUT output disable N-ch Push-pull output that can be output high impedance (both P-ch and N-ch are off). 11 PD70732 5 2. REGISTER SET The registers of the V810 can be classified into two types: general-purpose program register set and dedicated system register set. All registers are 32 bits wide. Program register sets 31 r0 r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 r13 r14 r15 r16 r17 r18 r19 r20 r21 r22 r23 r24 r25 r26 r27 r28 r29 r30 r31 String Destination Bit Offset String Source Bit Offset String Length String Destination String Source Link Pointer (lp) 31 ADTRE Address Trap Register 0 31 CHCW Cache Control Word 0 31 TKCW Task Control Word 0 31 PIR Processor ID Register 0 31 PSW Program Status Word 0 31 ECR Exception Cause Register 0 Zero Register Reserved for Address Generation Handler Stack Pointer (hp) Stack Pointer (sp) Global Pointer (gp) Text Pointer (tp) 31 FEPC FEPSW Fatal Error PC Fatal Error PSW 0 0 31 EIPC EIPSW Exception/Interrupt PC Exception/Interrupt PSW System register sets 0 31 PC Program Counter 0 12 PD70732 2.1 Program Register Set The program register set is composed of general-purpose registers and a program counter. (1) General-purpose registers Thirty-two general-purpose registers, r0 to r31, are available. All these registers can be used as data registers or address registers. Of these registers, r0 and r26 through r30 are implicitly used by some instructions, and r1 through r5 and r31 are implicitly used by the assembler and C compiler. Therefore, when using these registers, it is necessary to take special care such as saving these registers' contents to different areas before using these registers and restoring the contents after using them. Table 2-1. Program Registers Register r0 r1 r2 r3 r4 r5 r6 to r25 r26 r27 r28 r29 r30 r31 Zero register Register reserved for assembler Handler stack pointer Stack pointer Global pointer Text pointer -- String destination bit offset String source bit offset String length register String destination address register String address register Link pointer Stores the return address at execution of a JAL instruction. Application Always holds zeros. Used as a working register to generate a 32-bit immediate data. Used as the stack pointer for the handler. Used to generate a stack frame at a function call. Used to access a global variable in the data area. Points the start address of the text area. Stores address or data variables. Used in a bit-string instruction execution. Operation (2) Program Counter The program counter (PC) indicates the address of the instruction currently executed by the program. Bit 0 of the PC is fixed to 0, and execution cannot branch to an odd address. The contents of the PC are initialized to FFFFFFF0H at reset. 13 PD70732 2.2 System Register Set The system register set is composed of the following registers that perform operations such as CPU-status control and interrupt information holding. Table 2-2. System Register Number Number 0 Register Name EIPC Application Status saving registers for exception/interrupt Operation The EIPC and EIPSW registers save the PC and PSW, respectively, when an exception or interrupt occurs. Because in the V810 the registers incorporated for this purpose are these registers only, save the contents of these registers by means of programming if your application set can cause multiple interrupt requests to be issued in the V810. The FEPC and FEPSW registers save the PC and PSW, respectively, when an NMI or duplexed exception occurs. This register, when an exception, maskable interrupt, or NMI occurs, holds its cause. This register consists of 32 bits. Its higher 16 bits, called FECC, hold the exception code for an NMI or duplexed exception, while the lower 16 bits, called EICC, hold the exception code for an exception or maskable interrupt. 5 PSW Program status word This register, also called the program status word, is a set of flags indicating the statuses of the CPU and program (instruction execution results). This register identifies the CPU type number. This register controls floating-point operations. 1 EIPSW 2 3 4 FEPC FEPSW ECR Status saving registers for NMI/duplexed exception Exception cause register 6 7 8 to 23 24 25 PIR TKCW Reserved CHCW ADTRE Processor ID register Task control word Cache control word Address trap register This register controls the on-chip instruction cache. This register holds an address and is used for address trapping. When the address in this register matches the PC value, the execution jumps to a predefined address. 26 to 31 Reserved To read or write one of the registers shown above, specify a system register number with the system register load (LDSR) or system register store (STSR) instruction. 14 PD70732 3. DATA TYPES 5 3.1 Data Types The data types supported by the V810 are as follows: * Integer (8, 16, 32 bits) * Unsigned integer (8, 16, 32 bits) * Bit string * Single-precision floating-point data (32 bits) 3.1.1 Data type and addressing The V810 uses the little-endian data addressing. In this addressing, if a fixed-length data is located in a memory area, the data must be either of the data types shown below. (1) Byte A byte is a consecutive 8-bit data whose first-bit address is aligned to a byte boundary. Each bit in a byte is numbered from 0 to 7: LSB (the least significant bit) is bit 0 and MSB (the most significant bit) is bit 7. To access a byte, specify address A. (See diagram below.) 7 0 A (2) Halfword A halfword is a consecutive 16-bit (= 2 bytes) data whose first-bit address is aligned to a halfword boundary. Each bit in a halfword is numbered from 0 to 15: LSB (the least significant bit) is bit 0 and MSB (the most significant bit) is bit 15. To access a halfword, specify the address A only (lowest bit must be 0). 15 87 0 A+1 A (3) Word/short real A word, also called short real, is a consecutive 32-bit (= 4 bytes) data whose first-bit address is aligned to a word boundary. Each bit in a word is numbered from 0 to 31: LSB (the least significant bit) is bit 0 and MSB (the most significant bit) is bit 31. To access a word or short real, specify the address A only (lower two bits must be 0). 31 24 23 16 15 87 0 A+3 A+2 A+1 A 15 PD70732 3.1.2 Integer In the V810, all integers are expressed in the two's-complement binary notation, and are composed of either 8 bits, 16 bits, or 32 bits. Regardless of the data length, bit 0 is the least significant bit, and higher-numbered bits express higher digits of the integer with the highest bit expressing its sign. Data Length Byte Halfword Word 8 bits 16 bits 32 bits Range -128 to +127 -32768 to +32767 -2147483648 to +2147483647 3.1.3 Unsigned integer An unsigned integer is either zero or a positive integer unlike the integer explained in section 3.1.2 which can be negative as well as zero and positive. Unsigned integers are expressed in the binary notation in the same way as integers, and are either 8 bits, 16 bits, or 32 bits long. Regardless of the data length, the bit assignments are the same as in the case of integers except that unsigned integers do not include a sign bit; the highest bit is also a part of the integer. Data Length Byte Halfword Word 8 bits 16 bits 32 bits Range 0 to 255 0 to 65535 0 to 4294967295 3.1.4 Bit string A bit string is a type of data whose bit length is variable from 0 to 232 - 1. To specify a bit-string data, define the following three attributes. * A : address of the string data's first word (lower two bits must be 0.) * B : in-word bit offset in the string data (0 to 31) * M : bit length of the string data (0 to 232 - 1) The above three attributes may vary depending on the bit-string data manipulation direction: upward or downward, as shown below. The former is the direction from lower addresses to higher addresses while the latter is the direction from higher to lower addresses. M-1 M 0 A+8 D A+4 A (Word boundary) B Attribute First-word address (0s in bits 1 and 0) In-word bit offset (0 to 31) Bit length (0 to 2 - 1) 32 Upward A B M Downward A+4 D M 16 PD70732 3.1.5 Single-precision floating-point data This data type is 32 bits long and its bit allocation complies with the IEEE single format. A single-precision floating-point data consists of 1-bit mantissa sign bit, 8-bit exponent, and 23-bit mantissa. The exponent is offsetexpressed from the bias value - 127, and the mantissa is binary-expressed with the integer part omitted. 31 s 30 exp (8) 23 22 mantissa (23) 0 3.2 Data Alignment In the V810, a word data must be aligned to a word boundary (with the lowest two bits of the address fixed to 0s), and a halfword data to a halfword boundary (with the lowest bit of the address fixed to 0). If a data is not aligned as specified, the lowest one bit (in the case of word) or two bits (in the case of halfword) of its address will forcibly be masked with 0s when the data is accessed. 17 PD70732 5 4. ADDRESS SPACE The V810 supports 4 Gbytes of linear memory space and I/O space. The CPU outputs 32-bit addresses to the memory and I/Os; therefore, the addresses are from 0 to 232 - 1. Bit number 0 of each byte data is defined as the LSB (Least Significant Bit), and bit number 7 is the MSB (Most Significant Bit). Unless otherwise specified, the byte data at the lower address side of data consisting of two or more bytes is the LSB, and the byte data at the higher address side is the MSB (little endian). Data consisting of 2 bytes is called a halfword, and data consisting of 4 bytes is called a word. The lower address of memory or I/O data of two or more bytes, here, is shown on the right, and the higher address is shown on the left, as follows: Byte of address A 7 0 A (address) Halfword of address A 15 87 0 A+1 A (address) Word/short real of address A 31 24 23 16 15 87 0 A+3 A+2 A+1 A 18 PD70732 Figure 4-1 shows the memory map of the V810, and Figure 4-2 shows the I/O map. Figure 4-1. Memory Map FFFFFFFFH Interrupt handler tableNote FFFFFE00H FFFFFDFFH General use 00000000H Note For the details, refer to Table 6-1 Exception Codes. 19 PD70732 Figure 4-2. I/O Map FFFFFFFFH General use 00000000H 20 PD70732 5. BUS INTERFACE FUNCTION The V810 is equipped with a 32-bit data bus. In the bus interface, there are two modes: 32-bit bus mode which uses the data bus in 32 bits and 16-bit bus fixed mode which fixes the bus in 16 bits. Modes can be switched only at reset using the SIZ16B signal. The 32-bit bus mode has a dynamic bus sizing function which uses the data bus in 16-bit bus width to access the 16-bit peripherals. This function can be used by setting the SZRQ signal active. Access to word data (32-bit data) in the dynamic bus sizing is executed by loading/storing a 16-bit data twice. In the 16-bit bus fixed mode, access to word data (32-bit data) is executed by activating a bus cycle twice. The control signal and the A1 signal output values according to the 16-bit system. The relationship between the external access and byte enable signals (BE3 to BE0) during the 32-bit bus mode and the 16-bit bus fixed mode is shown below. Table 5-1. Relationship among Address, Data Length, Byte Enable Signals and A1 (32-bit bus mode) Operand address Data length Bit 1 Byte 0 0 1 1 Halfword 0 1 Word 0 Bit 0 0 1 0 1 0 0 0 BE3 1 1 1 0 1 0 0 0 BE2 1 1 0 1 1 0 0 0 BE1 1 0 1 1 0 1 0 1 BE0 0 1 1 1 0 1 0 1 0 0 0 0 0 0 0 1 2 Byte enable A1 Bus cycle sequence 1 1 1 1 1 1 1 Note 5 Note Bus cycle added by dynamic bus sizing Table 5-2. Relationship among Address, Data Length, Byte Enable Signals and A1 (16-bit bus fixed mode) Operand address Data length Bit 1 Byte 0 0 1 1 Halfword 0 1 Word 0 Bit 0 0 1 0 1 0 0 0 BE3 Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z BE2 Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z BE1 1 0 1 0 0 0 0 0 BE0 0 1 0 1 0 0 0 0 0 0 1 1 0 1 0 1 2 Byte enable A1 Bus cycle sequence 1 1 1 1 1 1 1 Note Note Added bus cycle 21 PD70732 5 6. INTERRUPT AND EXCEPTION Interrupts are events that take place independently of the program execution and can be classified into maskable interrupts and a non-maskable interrupt. An exception is an event that takes place depending upon the program execution. There is little difference between the interrupt and exception in terms of flow, but the interrupt takes precedence over the exception. The V810 architecture is provided with the interrupts and exceptions listed in the table below. If an exception, a maskable interrupt or NMI occurs, control is transferred to a handler whose address is determined by the source of the interrupt or exception. The exception source can be checked by examining an exception code stored in the ECR (Exception Code Register). Each handler analyzes the contents of the ECR and performs appropriate exception/interrupt servicing. Table 6-1. Exception Codes Exception and interrupt Reset NMI Duplexed exception Address trap Trap instruction (parameter is 0x1n) Trap instruction (parameter is 0x0n) Invalid instruction code Zero division FIV (floating-point invalid operation) FZD (floating-point zero division) FOV (floating-point overflow) FUD (floating-point underflow)Note 5 FPR (floating-point precision degradation)Note 5 FRO (floating-point reserved operand) INT level n (n = 0 to 15) Classification Interrupt Interrupt Exception Exception Exception Exception Exception Exception Exception Exception Exception Exception Exception Exception Interrupt Exception code FFF0 FFD0 Note 4 FFC0 FFBn FFAn FF90 FF80 FF70 FF68 FF64 FF62 FF61 FF60 FEn0 Handler address FFFFFFF0 FFFFFFD0 FFFFFFD0 FFFFFFC0 FFFFFFB0 FFFFFFA0 FFFFFF90 FFFFFF80 FFFFFF60 FFFFFF60 FFFFFF60 FFFFFF60 FFFFFF60 FFFFFF60 FFFFFEn0 Restore PCNote 1 Note 2 next PCNote 3 current PC current PC next PC next PC current PC current PC current PC current PC current PC current PC current PC current PC next PCNote 3 Notes 1. PC to be saved to EIPC or FEPC. 2. EIPC and FEPC are undefined. 3. While an instruction whose execution is aborted by an interrupt (DIV/DIVU, single-precision floatingpoint data, bit string instruction) is executed, restore PC = current PC. 4. The exception code of the exception that occurs for the first time is stored to the lower 16 bits of the ECR, and that of the second exception is stored in the higher 16 bits. 5. In the V810, the floating-point underflow exception and floating-point precision degradation exception do not occur. 22 PD70732 7. CACHE Figure 7-1 shows the instruction cache configuration provided to the V810. Figure 7-1. Cache Configuration Capacity Mapping system Block size Sub-block size : 1 Kbytes : direct map : 8 bytes : 4 bytes 5 31 Memory address TAG 10 9 Index 32 Offset 0 Tag memory (ICHT27 to ICHT0) Data memory (ICHD31 to ICHD0) 27 Entry 0 Entry 1 22 21 TAG31 to TAG10 0 31 Sub-block (4 bytes) 0 Block (8 bytes) 128 entries 128 blocks Entry 127 Valid bits (1 bit for every 4 bytes) NECRV (Reserved by NEC) 23 PD70732 5 8. RESET A low-level input detection on the RESET pin always triggers a system reset. Consequently, all the hardwarecontrolling registers are initialized as shown in Table 8-1. After the initialization procedure is completed and the RESET pin returns to the high level, the device is released from the resetting state and starts the implementation of a program. Then, if necessary, set some registers to user-desired values in the first stage of the program. Table 8-1. Register State after Reset Hardware (Symbol) Program counter Status saving register for interrupt PC EIPC EIPSW Status saving register for NMI FEPC FEPSW Interrupt cause register FECC EICC Program status word General-purpose register PSW r0 r1 to r31 0000H FFF0H 00008000H Fixed to 00000000H Undefind Undefind State after Reset FFFFFFF0H Undefind 24 PD70732 9. INSTRUCTION SET 5 9.1 Instruction Format The V810 instructions are formatted in either 16 bits or 32 bits. Examples of the 16-bit format instruction are binomial operation, control, and conditional branch; those for the 32-bit format are load/store, I/O manipulate, 16bit immediate, jump & link, and extended operations. Some instructions have an unused field. However, do not write a program that uses this field because it is reserved for future use. This unused field must be set to zeros. Instructions are stored in memory in the following manner. * The lower half of an instruction, that is, the half which includes bit 0, is stored at the lower address. * The higher half of an instruction, that is, the half which includes bit 15 or 31, is stored at the higher address. (1) reg-reg instruction format (Format I) This format consists of one 6-bit field to hold an operation code and two 5-bit fields to specify generalpurpose registers as instruction's operands. 16-bit instructions use this format. 15 opcode 10 9 reg2 54 reg1 0 (2) imm-reg instruction format (Format II) This format consists of one 6-bit field to hold an operation code, one 5-bit field to hold an immediate data, and one field to specify a general-purpose register as an operand. 16-bit instructions use this format. 15 opcode 10 9 reg2 54 imm 0 (3) Conditonal branch instruction format (Format III) This format consists of one 3-bit field to hold an operation code, one 4-bit field to hold a condition code, and one 9-bit field to hold a branch displacement (with its LSB masked to 0). 16-bit instructions use this format. 15 13 12 cond 98 disp 0 0 opcode 25 PD70732 (4) Intermediate jump instruction format (Format IV) This format consists of one 6-bit field to hold an operation code and one 26-bit field to hold a displacement (with its LSB masked to 0). 32-bit instructions use this format. 15 opcode 10 9 0 31 disp 16 0 (5) 3-operand instruction format (Format V) This format consists of one 6-bit field to hold an operation code, two fields to specify general-purpose registers as operands, and one 16-bit field to hold an immediate data. 32-bit instructions use this format. 15 opcode 10 9 reg2 54 reg1 0 31 imm 16 (6) Load/store instruction format (Format VI) This format consists of one 6-bit field to hold an operation code, two fields to specify a general-purpose register, and one 16-bit field to hold a displacement. 32-bit instructions use this format. 15 opcode 10 9 reg2 54 reg1 0 31 disp 16 (7) Extension instruction format (Format VII) This format consists of one 6-bit field to hold an operation code, two 5-bit fields to specify general-purpose registers as operands, and one 6-bit field to hold an sub-operation code. The remaining 10 bits are reserved for future use and must be set to zeros. 32-bit instructions use this format. 15 opcode 10 9 reg2 54 reg1 0 31 sub-opcode RFU 16 26 PD70732 9.2 Instruction Mnemonic (in alphabetical order) The list of mnemonics is shown below. This section lists the instructions incorporated in the V810 along with their operations. The instructions are listed in the instruction mnemonic's alphabetical order to allow users to use this section as a quick reference or dictionary. The conventions used in the list are shown below. Instruction Mnemonic Operand (s) Format CY OV S Z Instruction Function Legend ADD reg1, reg2 I * * * * Mnemonic of instruction Identifier of operand Instruction format (Refer to 9.1.) Flag operation - Remains unchanged * Inverts the previous value 0 Changes to 0 1 Changes to 1 Identifier reg1 reg2 imm5 imm16 disp9 disp16 disp26 regID vector adr Description General-purpose register (Used as a source register) General-purpose register (Used mainly as a destination register and occasionally as a source register) 5-bit immediate 16-bit immediate 9-bit displacement 16-bit displacement 26-bit displacement System register number Trap handler address that corresponds to a trap vector 27 PD70732 Table 9-1. Instruction Mnemonics (in alphabetical order) (1/9) Instruction Mnemonic ADD reg1, reg2 I * * * * Addition: Adds the word data in the reg2-specified register and the word data in the reg1-specified register, then stores the result into the reg2-specified register. Addition: Sign-extends the 5-bit immediate data to 32 bits, and adds the extended immediate data and the word data in the reg2-specified register, then stores the result into the reg2-specified register. Floating-point addition: Adds the single-precision floating-point data in the reg2-specified register and the single-precision floatingpoint data in the reg1-specified register, then restores the result into the reg2-specified register while changing flags according to the result. Addition: Sign-extends the 16-bit immediate data to 32 bits, and adds the extended immediate data and the word data in the reg1-specified register, then stores the result into the reg2-specified register. AND: Performs the logical AND operation on the word data in the reg2-specified register and the word data in the reg1-specified register, then stores the result into the reg2-specified register. Transfer after ANDing bit strings: Performs a logical AND operation on a source bit string and a destination bit string, then transfers the result to the destination bit string. AND: Sign-extends the 16-bit immediate data to 32 bits, and performs a logical AND operation on the extended immediate data and the word data in the reg1-specified register, then stores the result into the reg2-specified register. Transfer after NOTting a bit string then ANDing it with another bit string: Performs a logical AND operation on a destination bit string and the 1's complement of a source bit string, then transfers the result to the destination bit string. Conditional branch (if Carry): PC relative branch Conditional branch (if Equal): PC relative branch Conditional branch (if Greater than or Equal): PC relative branch Conditional branch (if Greater than): PC relative branch Operand (s) Format CY OV S Z Instruction Function ADD imm5, reg2 II * * * * ADDF.S reg1, reg2 VII * 0 * * ADDI imm16, reg1, reg2 V * * * * AND reg1, reg2 I - 0 * * ANDBSU - II - - - - ANDI imm16, reg1, reg2 V - 0 0 * ANDNBSU - II - - - - BC disp9 III - - - - BE disp9 III - - - - BGE disp9 III - - - - BGT disp9 III - - - - 28 PD70732 Table 9-1. Instruction Mnemonics (in alphabetical order) (2/9) Instruction Mnemonic BH disp9 III - - - - Conditional branch (if Higher): PC relative branch Conditional branch (if Lower): PC relative branch Conditional branch (if Less than or Equal): PC relative branch Conditional branch (if Less than): PC relative branch Conditional branch (if Negative): PC relative branch Conditional branch (if Not Carry): PC relative branch Conditional branch (if Not Equal): PC relative branch Conditional branch (if Not Higher): PC relative branch Conditional branch (if Not Lower): PC relative branch Conditional branch (if Not Overflow): PC relative branch Conditional branch (if Not Zero): PC relative branch Conditional branch (if Positive): PC relative branch Unconditional branch: PC relative branch Conditional branch (if Overflow): PC relative branch Conditional branch (if Zero): PC relative branch Inter-processor synchronization in a multi-processor system. Comparison: Subtracts the word data in the reg1-specified register from that for reg2 for comparison, then changes flags according to the result. Comparison: Sign-extends the 5-bit immediate data to 32 bits, and subtracts the extended immediate data from the word data in the reg2-specified register for comparison, then changes flags according to the result. Floating-point comparison: Subtracts the single-precision floating-point data in the reg1-specified register from that for reg2 for comparison, then changes flags according to the result. Operand (s) Format CY OV S Z Instruction Function BL disp9 III - - - - BLE disp9 III - - - - BLT disp9 III - - - - BN disp9 III - - - - BNC disp9 III - - - - BNE disp9 III - - - - BNH disp9 III - - - - BNL disp9 III - - - - BNV disp9 III - - - - BNZ disp9 III - - - - BP disp9 III - - - - BR disp9 III - - - - BV disp9 III - - - - BZ disp9 III - - - - CAXI CMP disp16 [reg1], reg2 reg1, reg2 VI I * * * * * * * * CMP imm5, reg2 II * * * * CMPF.S reg1, reg2 VII * 0 * * 29 PD70732 Table 9-1. Instruction Mnemonics (in alphabetical order) (3/9) Instruction Mnemonic CVT.SW reg1, reg2 VII - 0 * * Data conversion from floating-point to integer: Converts the single-precision floating-point data in the reg1-specified register into an integer data, then stores the result into the reg2-specified register while changing flags according to the result. Data conversion from integer to floating-point: Converts the integer data in the reg1-specified register into a single-precision floating-point data, then stores the result into the reg2-specified register while changing flags according to the result. Signed division: Divides the word data in the reg2-specified register by that for reg1 with their sign bits validated, then stores the quotient into the reg2-specified register and the remainder into r30. Division is performed so that the sign of the remainder matches that of the dividend. Floating-point division: Divides the single-precision floating-point data in the reg2-specified register by that for reg1, then stores the result into the reg2-specified register while changing flags according to the result. Unsigned division: Divides the word data in the reg2-specified register by that for reg1 with their data handled as unsigned data, then stores the quotient into the reg2-specified register and the remainder into r30. Division is performed so that the sign of the remainder matches that of the dividend. Processor stop Port input: Sign-extends the 16-bit displacement to 32 bits, and adds the extended displacement and the content of the reg1-specified register to generate a 32-bit unsigned port address, then reads the byte data located at the generated port address, zero-extends the byte data to 32 bits, and stores the result into the reg2-specified register. Port input: Sign-extends the 16-bit displacement to 32 bits, and adds the extended displacement and the content of the reg1-specified register to generate a 32-bit unsigned port address, then reads the halfword data located at the generated port address while masking the address's bit 0 to 0, zero-extends the halfword data to 32 bits, and stores the result into the reg2-specified register. Operand (s) Format CY OV S Z Instruction Function CVT.WS reg1, reg2 VII * 0 * * DIV reg1, reg2 I - * * * DIVF.S reg1, reg2 VII * 0 * * DIVU reg1, reg2 I - 0 * * HALT IN.B - disp16 [reg1], reg2 II VI - - - - - - - - IN.H disp16 [reg1], reg2 VI - - - - 30 PD70732 Table 9-1. Instruction Mnemonics (in alphabetical order) (4/9) Instruction Mnemonic IN.W disp16 [reg1], reg2 VI - - - - Port input: Sign-extends the 16-bit displacement to 32 bits, and adds the extended displacement and the content of the reg1-specified register to generate a 32-bit unsigned port address, then reads the word data located at the generated address while masking the address's bits 0 and 1 to 0, and stores the word into the reg2specified register. JAL disp26 IV - - - - Jump and link: Increments the current PC by 4, then saves it into r31, and sign-extends the 26-bit displacement to 32 bits while masking the displacement's bit 0 to 0, adds the extended displacement and the PC value, loads the PC with the addition result, so that the instruction stored at the PC-pointing address is executed next. JMP [reg1] I - - - - Register-indirect unconditional branch: Loads the PC with the jump address value in the reg1specified register while masking the value's bit 0 to 0, so that the instruction stored at the address pointed by the reg1-specified register is executed next. JR disp26 IV - - - - Unconditional branch: Sign-extends the 26-bit displacement to 32 bits while masking bit 0 to 0, adds the result with the current PC value, and loads the PC with the addition result so that the instruction stored at the PC-pointing address is executed next. LD.B disp16 [reg1], reg2 VI - - - - Byte load: Sign-extends the 16-bit displacement to 32 bits, and adds the result with the content of the reg1-specified register to generate the 32-bit unsigned address, then reads the byte data located at the generated address, sign-extends the byte data to 32 bits, and stores the result into the reg2-specified register. Halfword load: Sign-extends the 16-bit displacement to 32 bits, and adds the result with the content of the reg1-specified register to generate a 32-bit unsigned address while masking its bit 0 to 0, then reads the halfword data located at the generated address, sign-extends the halfword data to 32 bits, and stores the result into the reg2-specified register. Word load: Sign-extends the 16-bit displacement to 32 bits and adds the result with the content of the reg1-specified register to generate a 32-bit unsigned address while masking bits 0 and 1 to 0, then reads the word data located at the generated address and stores the data into the reg2-specified register. Operand (s) Format CY OV S Z Instruction Function LD.H disp16 [reg1], reg2 VI - - - - LD.W disp16 [reg1], reg2 VI - - - - 31 PD70732 Table 9-1. Instruction Mnemonics (in alphabetical order) (5/9) Instruction Mnemonic LDSR reg2, regID II * * * * Loading system register: Transfers the word data in the reg2-specified register to the system register specified with the system register number (regID). Transferring data: Loads the reg2-specified register with the word data in of the reg1-specified register. Transferring data: Sign-extends the 5-bit immediate data to 32 bits, then loads the reg2-specified register with the extended immediate data. Transferring bit strings: Loads the destination bit string with the source bit string. Addition: Sign-extends the 16-bit immediate data to 32 bits, adds it with the word data in the reg1-specified register, then stores the addition result into reg2. Addition: Appends 16-bit zeros below the 16-bit immediate data to form a 32-bit word data, then adds it with the word data in the reg1-specified register, and stores the result into the reg2-specified register. Signed multiplication: Signed-multiplies the word data in the reg2-specified register by that for reg1, then separates the 64-bit (double-word) result into two 32-bit data, and stores the higher 32 bits into r30 and the lower 32 bits into the reg2-specified register. Floating-point multiplication: Multiplies the single-precision floating-point data in the reg2-specified register by that for reg1, then stores the result into the reg2-specified register while changing flags according to the result. Unsigned multiplication: Multiplies the word data in the reg2-specified register by that for reg1 while handling these data as unsigned data, then separates the 64-bit (double-word) result into two 32-bit data, and stores the higher 32 bits into r30 and the lower 32 bits into the reg2-specified register. No operation: Makes no changes or operations while spending one instruction cycle. Logical NOT: Obtains the 1's complement (logical NOT) of the content of the reg1-specified register, then stores the result into the reg2-specified register. Operand (s) Format CY OV S Z Instruction Function MOV reg1, reg2 I - - - - MOV imm5, reg2 II - - - - MOVBSU - II - - - - MOVEA imm16, reg1, reg2 V - - - - MOVHI imm16, reg1, reg2 V - - - - MUL reg1, reg2 I - * * * MULF.S reg1, reg2 VII * 0 * * MULU reg1, reg2 I - * * * NOP - III - - - - NOT reg1, reg2 I - 0 * * 32 PD70732 Table 9-1. Instruction Mnemonics (in alphabetical order) (6/9) Instruction Mnemonic NOTBSU - II - - - - Transfer after NOTting a bit string: Obtains the 1's complement (all bits inverted) of the source bit string, then transfers the result to the destination bit string. OR: Performs a logical OR operation on the word data in the reg2-specified register and that for reg1, then stores the result into the reg2-specified register. Transfer after ORing bit strings: Performs a logical OR operation on the source and destination bit strings, then transfers the result to the destination bit string. OR: Zero-extends the 16-bit immediate data to 32 bits, performs a logical OR operation on the extended data and the word data in the reg1-specified register, then stores the result into the reg2-specified register. Transfer after NOTting a bit string and ORing it with another bit string: Obtains the 1's complement (logical NOT) of the source bit string, performs a logical OR operation on the NOTted bit string and the destination bit string, then transfers the result to the destination bit string. Port output: Sign-extends the 16-bit displacement to 32 bits, adds the extended value and the content of the reg1specified register to generate a 32-bit unsigned port address, then outputs the lowest 8 bits (= 1 byte) of the reg2-specified register onto the port pins corresponding to the generated port address. Port output: Sign-extends the 16-bit displacement to 32 bits, adds the extended value and the content of the reg1specified register to generate a 32-bit unsigned port address with its bit 0 masked to 0, then outputs the lowest 16 bits (= 1 halfword) of the reg2-specified register onto the port pins corresponding to the generated port address. Port output: Sign-extends the 16-bit displacement to 32 bits, adds the extended value and the content of the reg1specified register to generate a 32-bit unsigned port address with its bits 0 and 1 masked to 0, then outputs the 32 bits (= 1 word) of the reg2-specified register onto the port pins corresponding to the generated port address. Operand (s) Format CY OV S Z Instruction Function OR reg1, reg2 I - 0 * * ORBSU - II - - - - ORI imm16, reg1, reg2 V - 0 * * ORNBSU - II - - - - OUT.B reg2, disp16 [reg1] VI - - - - OUT.H reg2, disp16 [reg1] VI - - - - OUT.W reg2, disp16 [reg1] VI - - - - 33 PD70732 Table 9-1. Instruction Mnemonics (in alphabetical order) (7/9) Instruction Mnemonic RETI - II * * * * Return from a trap or interrupt routine: Reads the restore PC and PSW from the system registers and loads them to the due places to return from a trap or interrupt routine to the original operation flow. Arithmetic right shift: Shifts every bit of the word data in the reg2-specified register to the right by the number of times specified with the reg1-specified register's lowest 5 bits, then stores the result into the reg2-specified register. In arithmetic right shift operations, the MSB is loaded with the LSB value at each shift. Arithmetic right shift: Zero-extends the 5-bit immediate data to 32 bits, shifts every bit of the word data in the reg2-specified register to the right by the number of times specified with the extended immediate data, then stores the result into the reg2-specified register. In arithmetic right shift operations, the MSB is loaded with the LSB value at each shift. Searching 0s in a bit string: Searches "0" bits in the source bit string, and loads r30 and r27 with the address of the bit next to the first detected "0" bit, then r29 with the number of bits skipped until the first "0" bit is detected, and r28 with the value subtracted by the r29 value. Searching 1s in a bit string: Searches 1s in the source bit string, and loads r30 and r27 with the bit address next to the first detected "1" bit, then r29 with the number of bits skipped until the first "1" is detected, and r28 with the value subtracted by the r29 value. Flag condition setting: Sets the reg2-specified register to 1 if the condition flag value matches the lowest 4 bits of the 5-bit immediate data, and sets the reg2-specified register to 0 when they do not match. Logical left shift: Shifts every bit of the word data in the reg2-specified register to the left by the number of times specified with the reg1-specified register's lowest 5 bits, then stores the result into the reg2-specified register. In logical left shift operations, the LSB is loaded with 0 at each shift. Operand (s) Format CY OV S Z Instruction Function SAR reg1, reg2 I * 0 * * SAR imm5, reg2 II * 0 * * SCH0BSU SCH0BSD - - II II - - - - - - * * SCH1BSU SCH1BSD - - II II - - - - - - - - SETF imm5, reg2 II - - - - SHL reg1, reg2 I * 0 * * 34 PD70732 Table 9-1. Instruction Mnemonics (in alphabetical order) (8/9) Instruction Mnemonic SHL imm5, reg2 II * 0 * * Logical left shift: Zero-extends the 5-bit immediate data to 32 bits, shifts every bit of the word data in the reg2-specified register to the left by the number of times specified by the extended immediate data, then stores the result into the reg2-specified register. In logical left shift operations, the LSB is loaded with 0 at each shift. Logical right shift: Shifts every bit of the word data in the reg2-specified register to the right by the number of times specified with the reg1-specified register's lowest 5 bits, then stores the result into the reg2-specified register. In logical right shift operations, the MSB is loaded with 0 at each shift. Logical right shift: Zero-extends the 5-bit immediate data to 32 bits, shifts every bit of the word data in the reg2-specified register to the right by the number of times specified by the extended immediate data, then stores the result into the reg2-specified register. In logical right shift operations, the MSB is loaded with 0 at each shift. Byte store: Sign-extends the 16-bit displacement to 32 bits and adds the 32-bit displacement and the content of the reg1-specified register to generate a 32-bit unsigned address, then transfers the reg2-specified register's lowest 8 bits to the generated address. Halfword store: Sign-extends the 16-bit displacement to 32 bits with its bit 0 masked to 0, and adds the content of the reg1specified register and the 32-bit displacement to generate a 32-bit unsigned address, then transfers the reg2specified register's lower 16 bits to the generated address. Word store: Sign-extends the 16-bit displacement to 32 bits with its bits 0 and 1 masked to 0, and adds the reg1specified register and the 32-bit displacement to generate a 32-bit unsigned address, then transfers the content of the reg1-specified register to the generated address. Storing system register contents: Loads the reg2-specified register with the content of the system register specified by the system register number (regID). Subtraction: Subtracts the content of the reg1-specified register from the content of the reg2-specified register, then stores the result into the reg2-specified register. Operand (s) Format CY OV S Z Instruction Function SHR reg1, reg2 I * 0 * * SHR imm5, reg2 II * 0 * * ST.B reg2, disp16 [reg1] VI - - - - ST.H reg2, disp16 [reg1] VI - - - - ST.W reg2, disp16 [reg1] VI - - - - STSR regID, reg2 II - - - - SUB reg1, reg2 I * * * * 35 PD70732 Table 9-1. Instruction Mnemonics (in alphabetical order) (9/9) Instruction Mnemonic SUBF.S reg1, reg2 VII * 0 * * Floating-point subtraction: Subtracts the single-precision floating-point data in the reg1-specified register from that for reg2, then stores the result into the reg2-specified register while changing flags according to the result. Software trap: Jumps to a trap handler address according to the vector-specified trap vector (from 0 to 31) to start an exception handling after completing all necessary saving and presetting procedures as follows: (1) Saving the restore PC and PSW into the FEPC and FEPSW system registers, respectively, if the PSW's EP flag = 1, or into the EIPC and EIPSW system registers, respectively, if EP = 0 (2) Setting an exception code into the ECR's FECC and FESW flags if the PSW's EP flag = 1, or into the ECR's EICC if EP = 0 (3) Setting the PSW's ID flag and clearing the PSW's AE flag (4) Setting the PSW's NP flag if the PSW's EP flag = 1, or setting the PSW's ID flag if EP = 0 Conversion from floating-point data to integer: Converts the single-precision floating-point data in the reg1-specified register into an integer data, then stores the result into the reg2-specified register while changing flags according to the result. Exclusive OR: Performs a logical exclusive-OR operation on the word data in the reg2-specified register and that for reg1, then stores the result into the reg2-specified register. Transfer of exclusive ORed bit string: Performs a logical exclusive-OR operation on the source and destination bit strings, then transfers the result to the destination bit string. Exclusive OR: Zero-extends the 16-bit immediate data to 32 bits and performs a logical exclusive-OR operation on the extended immediate data and the word data in the reg2-specified register, then stores the result into the reg2-specified register. Transfer after exclusive-ORing a NOTted bit string and another bit string: Obtains the 1's complement (NOT) of the source bit string, and exclusive-ORs it with the destination bit string, then transfers the result to the destination bit string. Operand (s) Format CY OV S Z Instruction Function TRAP vector II - - - - TRNC.SW reg1, reg2 VII - 0 * * XOR reg1, reg2 I - 0 * * XORBSU - II - - - - XORI imm16, reg1, reg2 V - 0 * * XORNBSU - II - - - - 36 PD70732 10. ELECTRICAL SPECIFICATIONS Supported Electrical Specifications Operating Supply Voltage VDD = +5 V 10% Operating Ambient Temperature (TA) -10 to +70C -40 to +85C VDD = 2.7 to 3.6 V VDD = 2.2 to 3.6 V -40 to +85C -40 to +85C (16 MHz) -- -- -- PD70732-16 PD70732-20 120-pin Plastic QFP (20 MHz) -- -- -- (25 MHz) (20 MHz) (16 MHz) (10 MHz) PD70732-25 120-pin Plastic TQFP 176-pin Ceramic PGA (25 MHz) (20 MHz) (16 MHz) (10 MHz) (25 MHz) -- -- -- 5 Remarks 1. : with electrical specifications -- : without electrical specifications 2. ( ) : maximum operating frequency 37 PD70732 10.1 Specifications When VDD = +5 V 10% (1) TA = -10 to +70C Absolute Maximum Ratings (TA = 25C) Parameter Supply voltage Input voltage Clock Input voltage Output voltage Operating ambient temperature Storage temperature Symbol VDD VI VK VO TA Tstg VDD = +5 V 10% VDD = +5 V 10% VDD = +5 V 10% Test Conditions Rating -0.5 to +7.0 -0.5 to VDD + 0.3 -0.5 to VDD + 0.3 -0.5 to VDD + 0.3 -10 to +70 -65 to +150 Unit V V V V C C Cautions 1. Do not directly interconnect IC product output (or input/output) pins, or directly connect VDD or VCC to GND. However, open-drain pins and open-collector pins can be interconnected. Direct connection is also possible for an external circuit using timing design that avoids output collision with a pin that becomes high-impedance. 2. Product quality may suffer if the absolute maximum rating is exceeded for even a single parameter, or even momentarily. In other words, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore, the product must be used under conditions which ensure that the absolute maximum ratings are not exceeded. As far as possible, the product should be used in a state in which the rated value is not approached. The ratings and test conditions shown in the DC characteristics and AC characteristics are the normal operation and quality assurance ranges of the product. DC Characteristics (TA = -10 to +70C, VDD = +5V 10%) Parameter Clock input voltage, high Clock input voltage, low Input voltage, high Input voltage, low Output voltage, high Output voltage, low Input leak current, high Input leak current, low Output leak current, high Output leak current, low Supply current Symbol VKH VKL VIH VIL VOH VOL ILIH ILIL ILOH ILOL IDD IOH = -400 A IOL = 3.2 mA VIN = VDD VIN = 0 V VO = VDD VO = 0 V f = 16 MHz f = 20 MHz f = 25 MHz Stopping clock Note 1 Test Conditions MIN. 4.0 -0.5 2.2 -0.5 2.4 TYP. MAX. VDD + 0.3 +0.6 VDD + 0.3 +0.8 Unit V V V V V 0.45 10 -10 10 -10 64Note 2 80Note 2 100 Note 2 V A A A A 160 200 240 A mA 5 Notes 1. VIL = 0 V, VIH = VDD applied 2. In general benchmark test (Output pins are open.) Remark Operating supply current is approximately proportional to operating clock frequency. 38 PD70732 Capacitance (TA = 25C, VDD = +5 V 10%) Parameter Input capacitance I/O capacitance Symbol CI CIO Test Conditions fC = 1 MHz MIN. MAX. 15 15 Unit pF pF AC Characteristics (TA = -10 to +70C, VDD = +5V 10%) Clock Input Parameter Symbol Test Conditions Clock cycle Clock pulse high-level width Clock pulse low-level width Clock rise time Clock fall time tCYK tKKH tKKL tKR tKF PD70732-16 MIN. 62.5 26 26 5 5 MAX. PD70732-20 MIN. 50 21 21 4 4 MAX. PD70732-25 MIN. 40 17 17 3 3 MAX. ns ns ns ns ns Unit Reset Parameter Symbol Test Conditions RESET hold time (from VDD VALID) tHVR PD70732-16 MIN. 1000 + 20 tCYKR 62.5 26 26 10 10 10 20 tCYKR 1000 MAX. PD70732-20 MIN. 1000 + 20 tCYKR 50 21 21 10 10 10 20 tCYKR 1000 MAX. PD70732-25 MIN. 1000 + 20 tCYKR 40 17 17 10 10 10 20 tCYKR 1000 MAX. ns Unit Clock cycle (at reset) Clock high-level time (at reset) Clock low-level time (at reset) RESET setup time (to CLK, active) RESET setup time (to CLK, inactive) RESET hold time (from CLK) RESET pulse low-level width (to CLK) tCYKR tKKHR tKKLR tSRKF tSRKR tHKR tWRL ns ns ns ns ns ns ns 39 PD70732 Memory, I/O Access Parameter Symbol Test Conditions Address, etc. output delay time (from CLK) Address, etc. ouput hold time (from CLK) BCYST output delay time (from CLK) BCYST output hold time (from CLK) DA output delay time (from CLK) DA output hold time (from CLK) READY setup time (to CLK) READY hold time (from CLK) Data setup time (to CLK) Data hold time (from CLK) Data output delay time (from active, from CLK) Data output hold time (to active, from CLK) Data output delay time (from float, from CLK) Data output hold time (to float, from CLK) tHKDT 2 20 2 15 2 15 ns tDKA PD70732-16 MIN. 2 MAX. 20 PD70732-20 MIN. 2 MAX. 15 PD70732-25 MIN. 2 MAX. 15 ns Unit tHKA 2 20 2 15 2 15 ns tDKBC tHKBC tDKDA tHKDA tSRYK tHKRY tSDK tHKD tDKDT 2 2 2 2 6 5 6 5 2 20 20 20 20 2 2 2 2 5 5 5 5 15 15 15 15 2 2 2 2 4 4 4 4 15 15 15 15 ns ns ns ns ns ns ns ns 20 2 15 2 15 ns tLZKDT 5 25 5 20 5 20 ns tHZKDT 5 25 5 20 5 20 ns Dynamic Bus Sizing Parameter Symbol Test Conditions SZRQ setup time (to CLK) SZRQ hold time (from CLK) tSSZK tHKSZ PD70732-16 MIN. 6 5 MAX. PD70732-20 MIN. 5 5 MAX. PD70732-25 MIN. 4 4 MAX. ns ns Unit Interrupt Parameter Symbol Test Conditions NMI setup time (to CLK) NMI hold time (from CLK) INT, etc. setup time (to CLK) INT, etc. hold time (from CLK) tSNK tHKN tSIK tHKI PD70732-16 MIN. 6 5 6 5 MAX. PD70732-20 MIN. 5 5 5 5 MAX. PD70732-25 MIN. 4 4 4 4 MAX. ns ns ns ns Unit 40 PD70732 Bus Hold Parameter Symbol Test Conditions HLDRQ setup time (to CLK) HLDRQ hold time (from CLK) HLDAK output delay time (from CLK) HLDAK output hold time (from CLK) Address, etc. delay time (from active, from CLK) Address, etc. delay time (from float, from CLK) Data delay time (from active, from CLK) Data delay time (from float, from CLK) BCYST delay time (from active, from CLK) BCYST delay time (from float, from CLK) DA delay time (from active, from CLK) DA delay time (from float, from CLK) tLZKDA 2 25 2 20 2 20 ns tHZKDA 2 25 2 20 2 20 ns tSHQK tHKHQ tDKHA tHKHA tHZKA PD70732-16 MIN. 6 5 2 2 2 20 20 25 MAX. PD70732-20 MIN. 5 5 2 2 2 15 15 20 MAX. PD70732-25 MIN. 4 4 2 2 2 15 15 20 MAX. ns ns ns ns ns Unit tLZKA 2 25 2 20 2 20 ns tHZKD 5 25 5 20 5 20 ns tLZKD 5 25 5 20 5 20 ns tHZKBC 2 25 2 20 2 20 ns tLZKBC 2 25 2 20 2 20 ns AC Test Input Waveform (Except CLK) 2.2 V 0.8 V Test points 2.2 V 0.8 V AC Test Input Waveform (CLK) 4.0 V 3.0 V 1.7 V tKF Test points 3.0 V 1.7 V tKR 0.6 V AC Test Output Test Points 2.4 V 0.45 V Test points 2.4 V 0.45 V 41 PD70732 Load Conditions V810 output pin CL = 100 pF 42 PD70732 (2) TA = -40 to +85C Absolute Maximum Ratings (TA = 25C) Parameter Supply voltage Input voltage Clock Input voltage Output voltage Operating ambient temperature Storage temperature Symbol VDD VI VK VO TA Tstg VDD = +5 V 10% VDD = +5 V 10% VDD = +5 V 10% Test Conditions Rating -0.5 to +7.0 -0.5 to VDD + 0.3 -0.5 to VDD + 0.3 -0.5 to VDD + 0.3 -40 to +85 -65 to +150 Unit V V V V C C Cautions 1. Do not directly interconnect IC product output (or input/output) pins, or directly connect VDD or VCC to GND. However, open-drain pins and open-collector pins can be interconnected. Direct connection is also possible for an external circuit using timing design that avoids output collision with a pin that becomes high-impedance. 2. Product quality may suffer if the absolute maximum rating is exceeded for even a single parameter, or even momentarily. In other words, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore, the product must be used under conditions which ensure that the absolute maximum ratings are not exceeded. As far as possible, the product should be used in a state in which the rated value is not approached. The ratings and test conditions shown in the DC characteristics and AC characteristics are the normal operation and quality assurance ranges of the product. DC Characteristics (TA = -40 to +85C, VDD = +5V 10%) Parameter Clock input voltage, high Clock input voltage, low Input voltage, high Input voltage, low Output voltage, high Output voltage, low Input leak current, high Input leak current, low Output leak current, high Output leak current, low Supply current Symbol VKH VKL VIH VIL VOH VOL ILIH ILIL ILOH ILOL IDD IOH = -400 A IOL = 3.2 mA VIN = VDD VIN = 0 V VO = VDD VO = 0 V f = 20 MHz Stopping clock Note 1 Test Conditions MIN. 4.0 -0.5 2.2 -0.5 2.4 TYP. MAX. VDD + 0.3 +0.6 VDD + 0.3 +0.8 Unit V V V V V 0.45 10 -10 10 -10 80 Note 2 V A A A A mA A 200 5 Notes 1. VIL = 0 V, VIH = VDD applied 2. In general benchmark test (Output pins are open.) Remark Operating supply current is approximately proportional to operating clock frequency. 43 PD70732 Capacitance (TA = 25C, VDD = +5 V 10%) Parameter Input capacitance I/O capacitance Symbol CI CIO Test Conditions fC = 1 MHz MIN. MAX. 15 15 Unit pF pF AC Characteristics (TA = -40 to +85C, VDD = +5V 10%) Clock Input Parameter Symbol Test Conditions MIN. Clock cycle Clock pulse high-level width Clock pulse low-level width Clock rise time Clock fall time tCYK tKKH tKKL tKR tKF 50 21 21 4 4 PD70732-25 MAX. ns ns ns ns ns Unit Reset Parameter Symbol Test Conditions MIN. RESET hold time (from VDD VALID) Clock cycle (at reset) Clock high-level time (at reset) Clock low-level time (at reset) RESET setup time (to CLK, active) RESET setup time (to CLK, inactive) RESET hold time (from CLK) RESET pulse low-level width (to CLK) tHVR tCYKR tKKHR tKKLR tSRKF tSRKR tHKR tWRL 1000 + 20 tCYKR 50 21 21 10 10 10 20 tCYKR 1000 PD70732-25 MAX. ns ns ns ns ns ns ns ns Unit 44 PD70732 Memory, I/O Access Parameter Symbol Test Conditions MIN. Address, etc. ouput delay time (from CLK) Address, etc. ouput hold time (from CLK) BCYST output delay time (from CLK) BCYST output hold time (from CLK) DA output delay time (from CLK) DA output hold time (from CLK) READY setup time (to CLK) READY hold time (from CLK) Data setup time (to CLK) Data hold time (from CLK) Data output delay time (from active, from CLK) Data output hold time (to active, from CLK) Data output delay time (from float, from CLK) Data output hold time (to float, from CLK) tDKA tHKA tDKBC tHKBC tDKDA tHKDA tSRYK tHKRY tSDK tHKD tDKDT tHKDT tLZKDT tHZKDT 1 1 1 1 1 1 5 5 5 5 1 1 5 5 15 15 20 20 PD70732-25 MAX. 15 15 15 15 15 15 ns ns ns ns ns ns ns ns ns ns ns ns ns ns Unit Dynamic Bus Sizing Parameter Symbol Test Conditions MIN. SZRQ setup time (to CLK) SZRQ hold time (from CLK) tSSZK tHKSZ 5 5 PD70732-25 MAX. ns ns Unit Interrupt Parameter Symbol Test Conditions MIN. NMI setup time (to CLK) NMI hold time (from CLK) INT, etc. setup time (to CLK) INT, etc. hold time (from CLK) tSNK tHKN tSIK tHKI 5 5 5 5 PD70732-25 MAX. ns ns ns ns Unit 45 PD70732 Bus Hold Parameter Symbol Test Conditions MIN. HLDRQ setup time (to CLK) HLDRQ hold time (from CLK) HLDAK output delay time (from CLK) HLDAK output hold time (from CLK) Address, etc. delay time (from active, from CLK) Address, etc. delay time (from float, from CLK) Data delay time (from active, from CLK) Data delay time (from float, from CLK) BCYST delay time (from active, from CLK) BCYST delay time (from float, from CLK) DA delay time (from active, from CLK) DA delay time (from float, from CLK) tSHQK tHKHQ tDKHA tHKHA tHZKA tLZKA tHZKD tLZKD tHZKBC tLZKBC tHZKDA tLZKDA 5 5 1 1 2 2 5 5 2 2 2 2 15 15 20 20 20 20 20 20 20 20 PD70732-25 MAX. ns ns ns ns ns ns ns ns ns ns ns ns Unit AC Test Input Waveform (Except CLK) 2.2 V 0.8 V Test points 2.2 V 0.8 V AC Test Input Waveform (CLK) 4.0 V 3.0 V 1.7 V tKF Test points 3.0 V 1.7 V tKR 0.6 V AC Test Output Test Points 2.4 V 0.45 V Test points 2.4 V 0.45 V Load Conditions V810 output pin CL = 100 pF 46 PD70732 10.2 Specifications When VDD = 2.7 to 3.6 V Absolute Maximum Ratings (TA = 25C) Parameter Supply voltage Input voltage Clock Input voltage Output voltage Operaitng ambient temperature Storage temperature Symbol VDD VI VK VO TA Tstg VDD = 2.7 to 3.6 V VDD = 2.7 to 3.6 V VDD = 2.7 to 3.6 V Test Conditions Rating -0.5 to +7.0 -0.5 to VDD + 0.3 -0.5 to VDD + 0.3 -0.5 to VDD + 0.3 -40 to +85 -65 to +150 Unit V V V V C C Cautions 1. Do not directly interconnect IC product output (or input/output) pins, or directly connect VDD or VCC to GND. However, open-drain pins and open-collector pins can be interconnected. Direct connection is also possible for an external circuit using timing design that avoids output collision with a pin that becomes high-impedance. 2. Product quality may suffer if the absolute maximum rating is exceeded for even a single parameter, or even momentarily. In other words, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore, the product must be used under conditions which ensure that the absolute maximum ratings are not exceeded. As far as possible, the product should be used in a state in which the rated value is not approached. The ratings and test conditions shown in the DC characteristics and AC characteristics are the normal operation and quality assurance ranges of the product. DC Characteristics (TA = -40 to +85C, VDD = 2.7 to 3.6 V) Parameter Clock input voltage, high Clock input voltage, low Input voltage, high Input voltage, low Output voltage, high Symbol VKH VKL VIH VIL VOH IOH = -2.0 mA IOH = -100 A Output voltage, low Input leak current, high Input leak current, low Output leak current, high Output leak current, low Supply current VOL ILIH ILIL ILOH ILOL IDD IOL = 3.2 mA VIN = VDD VIN = 0 V VO = VDD VO = 0 V f = 16 MHz Stopping clockNote 1 38 Note 2 Test Conditions MIN. 0.8 VDD -0.5 2.0 -0.5 0.85 VDD VDD - 0.2 TYP. MAX. VDD + 0.3 +0.2 VDD VDD + 0.3 +0.6 Unit V V V V V V 0.4 5 -5 5 -5 100 30 V A A A A mA A 3 Notes 1. VIL = 0 V, VIH = VDD applied 2. In general benchmark test (Output pins are open.) Remark Operating supply current is approximately proportional to operating clock frequency. 47 PD70732 Capacitance (TA = 25C, VDD = 2.7 to 3.6 V) Parameter Input capacitance I/O capacitance Symbol CI CIO Test Conditions fC = 1 MHz MIN. MAX. 15 15 Unit pF pF AC Characteristics (TA = -40 to +85C, VDD = 2.7 to 3.6 V) Clock Input Parameter Symbol Test Conditions MIN. Clock cycle Clock pulse high-level width Clock pulse low-level width Clock rise time Clock fall time tCYK tKKH tKKL tKR tKF 62.5 26 26 5 5 PD70732-25 MAX. ns ns ns ns ns Unit Reset Parameter Symbol Test Conditions MIN. RESET hold time (from VDD VALID) Clock cycle (at reset) Clock high-level time (at reset) Clock low-level time (at reset) RESET setup time (to CLK, active) RESET setup time (to CLK, inactive) RESET hold time (from CLK) RESET pulse low-level width (to CLK) tHVR tCYKR tKKHR tKKLR tSRKF tSRKR tHKR tWRL 1000 + 20tCYKR 62.5 26 26 10 10 10 20tCYKR 1000 PD70732-25 MAX. ns ns ns ns ns ns ns ns Unit 48 PD70732 Memory, I/O Access Parameter Symbol Test Conditions MIN. Address etc. output delay time (from CLK) Address etc. output hold time (from CLK) BCYST output delay time (from CLK) BCYST output hold time (from CLK) DA output delay time (from CLK) DA output hold time (from CLK) READY setup time (to CLK) READY hold time (from CLK) Data setup time (to CLK) Data hold time (from CLK) Data output delay time (from active, from CLK) Data output hold time (to active, from CLK) Data output delay time (from float, from CLK) Data output hold time (to float, from CLK) tDKA tHKA tDKBC tHKBC tDKDA tHKDA tSRYK tHKRY tSDK tHKD tDKDT tHKDT tLZKDT tHZKDT 1 1 1 1 1 1 8 5 8 5 1 1 3 3 35 35 40 40 PD70732-25 MAX. 25 25 25 25 25 25 ns ns ns ns ns ns ns ns ns ns ns ns ns ns Unit Dynamic Bus Sizing Parameter Symbol Test Conditions MIN. SZRQ setup time (to CLK) SZRQ hold time (from CLK) tSSZK tHKSZ 8 5 PD70732-25 MAX. ns ns Unit Interrupt Parameter Symbol Test Conditions MIN. NMI setup time (to CLK) NMI hold time (from CLK) INT etc. setup time (to CLK) INT etc. hold time (from CLK) tSNK tHKN tSIK tHKI 8 5 8 5 PD70732-25 MAX. ns ns ns ns Unit 49 PD70732 Bus Hold Parameter Symbol Test Conditions MIN. HLDRQ setup time (to CLK) HLDRQ hold time (from CLK) HLDAK output delay time (from CLK) HLDAK output hold time (from CLK) Address, etc. delay time (from active, from CLK) Address, etc. delay time (from float, from CLK) Data delay time (from active, from CLK) Data delay time (from float, from CLK) BCYST delay time (from active, from CLK) BCYST delay time (from float, from CLK) DA delay time (from active, from CLK) DA delay time (from float, from CLK) tSHQK tHKHQ tDKHA tHKHA tHZKA tLZKA tHZKD tLZKD tHZKBC tLZKBC tHZKDA tLZKDA 8 5 1 1 3 3 3 3 3 3 3 3 25 25 30 30 40 40 30 30 30 30 PD70732-25 MAX. ns ns ns ns ns ns ns ns ns ns ns ns Unit AC Test Input Waveform (Except CLK) 2.0 V 0.6 V Test points 2.0 V 0.6 V AC Test Input Waveform (CLK) 0.8 VDD 0.7 VDD 0.3 VDD tKF Test points 0.7 VDD 0.3 VDD tKR 0.2 VDD AC Test Output Test Points 0.85 VDD 0.4 V Test points 0.85 VDD 0.4 V Load Conditions V810 output pin CL = 100 pF 50 PD70732 10.3 Specifications When VDD = 2.2 to 3.6 V Absolute Maximum Ratings (TA = 25C) Parameter Supply voltage Input voltage Clock Input voltage Output voltage Operaitng ambient temperature Storage temperature Symbol VDD VI VK VO TA Tstg VDD = 2.2 to 3.6 V VDD = 2.2 to 3.6 V VDD = 2.2 to 3.6 V Test Conditions Rating -0.5 to +7.0 -0.5 to VDD + 0.3 -0.5 to VDD + 0.3 -0.5 to VDD + 0.3 -40 to +85 -65 to +150 Unit V V V V C C Cautions 1. Do not directly interconnect IC product output (or input/output) pins, or directly connect VDD or VCC to GND. However, open-drain pins and open-collector pins can be interconnected. Direct connection is also possible for an external circuit using timing design that avoids output collision with a pin that becomes high-impedance. 2. Product quality may suffer if the absolute maximum rating is exceeded for even a single parameter, or even momentarily. In other words, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore, the product must be used under conditions which ensure that the absolute maximum ratings are not exceeded. As far as possible, the product should be used in a state in which the rated value is not approached. The ratings and test conditions shown in the DC characteristics and AC characteristics are the normal operation and quality assurance ranges of the product. DC Characteristics (TA = -40 to +85C, VDD = 2.2 to 3.6 V) Parameter Clock input voltage, high Clock input voltage, low Input voltage, high Symbol VKH VKL VIH VDD 2.5 V VDD 2.5 V Input voltage, low Output voltage, high VIL VOH IOH = -2.0 mA IOH = -100 A Output voltage, low Input leak current, high Input leak current, low Output leak current, high Output leak current, low Supply current VOL ILIH ILIL ILOH ILOL IDD IOL = 3.2 mA VIN = VDD VIN = 0 V VO = VDD VO = 0 V f = 10 MHz Stopping clockNote 1 24Note 2 3 Test Conditions MIN. 0.8 VDD -0.5 2.0 0.8 VDD -0.5 0.85 VDD VDD - 0.2 0.4 5 -5 5 -5 70 30 TYP. MAX. VDD + 0.3 +0.2 VDD VDD + 0.3 VDD + 0.3 +0.2 VDD Unit V V V V V V V V A A A A mA A Notes 1. VIL = 0 V, VIH = VDD applied 2. In general benchmark test (Output pins are open.) Remark Operating supply current is approximately proportional to operating clock frequency. 51 PD70732 Capacitance (TA = 25C, VDD = 2.2 to 3.6 V) Parameter Input capacitance I/O capacitance Symbol CI CIO Test Conditions fC = 1 MHz MIN. MAX. 15 15 Unit pF pF AC Characteristics (TA = -40 to +85C, VDD = 2.2 to 3.6 V) Clock Input Parameter Symbol Test Conditions MIN. Clock cycle Clock pulse high-level width Clock pulse low-level width Clock rise time Clock fall time tCYK tKKH tKKL tKR tKF 100 40 40 10 10 PD70732-25 MAX. ns ns ns ns ns Unit Reset Parameter Symbol Test Conditions MIN. RESET hold time (from VDD VALID) Clock cycle (at reset) Clock high-level time (at reset) Clock low-level time (at reset) RESET setup time (to CLK, active) RESET setup time (to CLK, inactive) RESET hold time (from CLK) RESET pulse low-level width (to CLK) tHVR tCYKR tKKHR tKKLR tSRKF tSRKR tHKR tWRL 1000 + 20tCYKR 100 40 40 10 10 15 20tCYKR 1000 PD70732-25 MAX. ns ns ns ns ns ns ns ns Unit 52 PD70732 Memory, I/O Access Parameter Symbol Test Conditions MIN. Address, etc. output delay time (from CLK) Address, etc. output hold time (from CLK) BCYST output delay time (from CLK) BCYST output hold time (from CLK) DA output delay time (from CLK) DA output hold time (from CLK) READY setup time (to CLK) READY hold time (from CLK) Data setup time (to CLK) Data hold time (from CLK) Data output delay time (from active, from CLK) Data output hold time (to active, from CLK) Data output delay time (from float, from CLK) Data output hold time (to float, from CLK) tDKA tHKA tDKBC tHKBC tDKDA tHKDA tSRYK tHKRY tSDK tHKD tDKDT tHKDT tLZKDT tHZKDT 1 1 1 1 1 1 15 5 15 5 1 1 3 3 50 50 50 50 PD70732-25 MAX. 35 35 35 35 35 35 ns ns ns ns ns ns ns ns ns ns ns ns ns ns Unit Dynamic Bus Sizing Parameter Symbol Test Conditions MIN. SZRQ setup time (to CLK) SZRQ hold time (from CLK) tSSZK tHKSZ 15 5 PD70732-25 MAX. ns ns Unit Interrupt Parameter Symbol Test Conditions MIN. NMI setup time (to CLK) NMI hold time (from CLK) INT, etc. setup time (to CLK) INT, etc. hold time (from CLK) tSNK tHKN tSIK tHKI 15 5 15 5 PD70732-25 MAX. ns ns ns ns Unit 53 PD70732 Bus Hold Parameter Symbol Test Conditions MIN. HLDRQ setup time (to CLK) HLDRQ hold time (from CLK) HLDAK output delay time (from CLK) HLDAK output hold time (from CLK) Address, etc. delay time (from active, from CLK) Address, etc. delay time (from float, from CLK) Data delay time (from active, from CLK) Data delay time (from float, from CLK) BCYST delay time (from active, from CLK) BCYST delay time (from float, from CLK) DA delay time (from active, from CLK) DA delay time (from float, from CLK) tSHQK tHKHQ tDKHA tHKHA tHZKA tLZKA tHZKD tLZKD tHZKBC tLZKBC tHZKDA tLZKDA 15 5 1 1 3 3 3 3 3 3 3 3 35 35 35 35 50 50 35 35 35 35 PD70732-25 MAX. ns ns ns ns ns ns ns ns ns ns ns ns Unit AC Test Input Waveform (Except CLK) 0.8 VDD 0.2 VDD Test points 0.8 VDD 0.2 VDD AC Test Input Waveform (CLK) 0.8 VDD 0.7 VDD 0.3 VDD tKF Test points 0.7 VDD 0.3 VDD tKR 0.2 VDD AC Test Output Test Points 0.85 VDD 0.4 V Test points 0.85 VDD 0.4 V Load Conditions V810 output pin CL = 100 pF 54 PD70732 Clock Timing tCYK tKKH tKF tKR CLK tKKL Reset Timing 0.9 VDD VDD tHVR tCYKR tKKHR tKKLR CLK tWRL tSRKF RESET tHKR tSRKR Clock stopping exception period 55 PD70732 Memory, I/O Access Timing T1 T2 T2 CLK tDKA tHKA Note tDKBC tHKBC BCYST tHKDA tDKDA tHKDA DA tSRYK tHKRY tSRYK tHKRY READY tSDK D31 to D0 (Read) tLZKDT D31 to D0 (Write) Hi-Z Hi-Z tHKD Hi-Z tHZKDT Hi-Z tDKDT D31 to D0 (Write) tHKDT Note A31 to A1, BE3 to BE0, R/W, MRQ, ST1, ST0, BLOCK, ADRSERR 56 PD70732 Dynamic Bus Sizing Timing T2 CLK tSSZK tHKSZ SZRQ Interrupt Timing CLK tSNK tHKN NMI tSIK tHKI INT, INTV3 to INTV0 57 58 Bus Hold Timing T1 T2 TI TH TH TH TI T1 CLK tSHQK tHKHQ tSHQK HLDRQ tDKHA tHKHA HLDAK tHZKA Note 1 Note 2 tLZKA tHZKD D31 to D0 (Write) tHZKBC BCYST Note 2 tLZKBC tLZKD tHZKDA DA tLZKDA Notes 1. A31 to A1, BE3 to BE0, R/W, MRQ, ST1, ST0 2. The level immediately before the high-impedance state has been stored internally. Remark A dashed line indicates high impedance. PD70732 PD70732 11. PACKAGE DRAWINGS 120-pin plastic QFP (28 x 28) A B 90 91 61 60 detail of lead end C D S 120 1 31 30 F G J H I M K P M N NOTE Each lead centerline is located within 0.15 mm (0.006 inch) of its true position (T.P.) at maximum material condition. L ITEM A B C D F G H I J K L M N P Q R S MILLIMETERS 32.00.3 28.00.2 28.00.2 32.00.3 2.4 2.4 0.350.10 0.15 0.8 (T.P.) 2.00.2 0.80.2 0.15 +0.10 -0.05 0.1 3.2 0.10.1 55 INCHES 1.2600.012 1.102 +0.009 -0.008 1.102 +0.009 -0.008 1.2600.012 0.094 0.094 0.014 +0.004 -0.005 0.006 0.031 (T.P.) 0.079 +0.009 -0.008 0.031 +0.009 -0.008 0.006 +0.004 -0.003 0.004 0.126 0.0040.004 55 3.5 MAX. 0.138 MAX. P120GD-80-LBB, MBB-1 Q R 59 PD70732 5 120-pin plastic TQFP (Fine pitch) (14 x 14) A B 90 91 61 60 detail of lead end C D S Q 120 1 31 30 F G H IM J K P N L S120GC-40-9EV NOTE Each lead centerline is located within 0.09 mm (0.004 inch) of its true position (T.P.) at maximum material condition. ITEM A B C D F G H I J K L M N P Q S MILLIMETERS 16.0 0.2 14.0 0.2 14.0 0.2 16.0 0.2 1.2 1.2 0.18 0.05 0.09 0.4 (T.P.) 1.0 0.2 0.5 0.2 0.145 0.05 0.08 1.0 0.1 0.1 0.05 1.2 MAX. M INCHES 0.630 0.008 0.551 +0.009 -0.008 0.551 +0.009 -0.008 0.630 0.008 0.047 0.047 0.007 0.002 0.004 0.016 (T.P.) 0.039 +0.009 -0.008 0.020 +0.008 -0.009 0.006 +0.002 -0.003 0.003 0.039 +0.005 -0.004 0.004 0.002 0.048 MAX. 60 3 +7 -3 PD70732 176-pin ceramic PGA (Seamweld) A (Bottom View) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 QPNML K J HGFEDCBA Index mark Orientation pin J G H I K L M M F E ITEM A MILLIMETERS 38.10.4 38.10.4 1.27 2.54 (T.P.) 2.80.3 0.5 MIN. 2.81 4.57 MAX. INCHES 1.500 +0.016 -0.015 1.500 +0.016 -0.015 0.050 0.100 (T.P.) 0.110 +0.012 -0.011 0.019 MIN. 0.111 0.180 MAX. D NOTE Each lead centerline is located within 0.5 mm ( 0.020 inch) of its true position (T.P.) at maximum material condition. D E F G H I J K L M 1.20.2 0.460.05 0.5 0.047 +0.008 -0.007 0.018 +0.002 -0.001 0.020 X176R-100A-1 61 PD70732 12. RECOMMENDED SOLDERING CONDITIONS The PD70732 should be soldered and mounted under the conditions recommended in the table below. For details of recommended soldering conditions, refer to the information document "Semiconductor Device Mounting Technology Manual" (C10535E). For soldering methods and conditions other than those recommended below, contact an NEC sales representative. Table 12-1. Surface Mounting Type Soldering Conditions (1) PD70732GD-16-LBB : 120-pin plastic QFP (28 x 28 mm) PD70732GD-20-LBB : 120-pin plastic QFP (28 x 28 mm) PD70732GD-25-LBB : 120-pin plastic QFP (28 x 28 mm) E specification model only Soldering Method Soldering Conditions Recommended Condition Symbol IR35-367-2 Infrared reflow Package peak temperature: 235C, Duration: 30 sec. Max. (at 210C or above), Number of times: Twice Max., Time limit: 7 days Note (thereafter 36 hours prebaking required at 125C) Package peak temperature: 215C, Duration: 40 sec. Max. (at 200C or above), Number of times: Twice Max., Time limit: 7 days Note (thereafter 36 hours prebaking required at 125C) Solder bath temperature: 260C Max., Duration: 10 sec. Max., Number of times: Once, Time limit: 7 days Note (thereafter 36 hours prebaking required at 125C), Preliminary heat temperature: 120C Max. (Package surface temperature) Pin temperature: 300C Max., Duration: 3 sec. Max. (per device side) VPS VP15-367-2 Wave soldering WS60-367-1 Partial heating -- Note For the storage period after dry-pack decapsulation, storage conditions are Max. 25C, 65% RH. Use of more than one soldering method should be avoided (except for partial heating). Caution 62 PD70732 (2) PD70732GC-25-9EV: 120-pin plastic TQFP (Fine pitch) (14 x 14 mm) Soldering Conditions Recommended Condition Symbol IR35-107-2 5 Soldering Method Infrared reflow Package peak temperature: 235C, Duration: 30 sec. Max. (at 210C or above), Number of times: Twice Max., Time limit: 7 days Note (thereafter 10 hours prebaking required at 125C) Package peak temperature: 215C, Duration: 40 sec. Max. (at 200C or above), Number of times: Twice Max., Time limit: 7 days Note (thereafter 10 hours prebaking required at 125C) Pin temperature: 300C Max., Duration: 3 sec. Max. (per device side) VPS VP15-107-2 Partial heating -- Note For the storage period after dry-pack decapsulation, storage conditions are Max. 25C, 65% RH. Use of more than one soldering method should be avoided (except for partial heating). Table 12-2. Insertion Type Soldering Conditions Caution PD70732R-25: 176-pin ceramic PGA (Seam weld) Soldering Method Wave soldering (Pin only) Partial heating Pin temperature: 300C Max., Duration: 3 sec. Max. (per one pin) Soldering Conditions Solder bath temperature: 260C Max., Duration: 10 sec. Max. Caution Apply wave soldering only to the pins and be careful not to bring solder into direct contact with the package. 63 PD70732 NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function. 64 PD70732 Regional Information Some information contained in this document may vary from country to country. Before using any NEC product in your application, please contact the NEC office in your country to obtain a list of authorized representatives and distributors. They will verify: * Device availability * Ordering information * Product release schedule * Availability of related technical literature * Development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, AC supply voltages, and so forth) * Network requirements In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country. NEC Electronics Inc. (U.S.) Mountain View, California Tel: 800-366-9782 Fax: 800-729-9288 NEC Electronics (Germany) GmbH Benelux Office Eindhoven, The Netherlands Tel: 040-2445845 Fax: 040-2444580 NEC Electronics Hong Kong Ltd. Hong Kong Tel: 2886-9318 Fax: 2886-9022/9044 NEC Electronics (Germany) GmbH Duesseldorf, Germany Tel: 0211-65 03 02 Fax: 0211-65 03 490 NEC Electronics Hong Kong Ltd. NEC Electronics (France) S.A. France Tel: 01-30-67 58 00 Fax: 01-30-67 58 99 Seoul Branch Seoul, Korea Tel: 02-528-0303 Fax: 02-528-4411 NEC Electronics (UK) Ltd. Milton Keynes, UK Tel: 01908-691-133 Fax: 01908-670-290 NEC Electronics (France) S.A. Spain Office Madrid, Spain Tel: 01-504-2787 Fax: 01-504-2860 NEC Electronics Singapore Pte. Ltd. United Square, Singapore 1130 Tel: 253-8311 Fax: 250-3583 NEC Electronics Italiana s.r.1. Milano, Italy Tel: 02-66 75 41 Fax: 02-66 75 42 99 NEC Electronics Taiwan Ltd. NEC Electronics (Germany) GmbH Scandinavia Office Taeby Sweden Tel: 8-63 80 820 Fax: 8-63 80 388 Taipei, Taiwan Tel: 02-719-2377 Fax: 02-719-5951 NEC do Brasil S.A. Sao Paulo-SP, Brasil Tel: 011-889-1680 Fax: 011-889-1689 J96. 3 65 PD70732 Reference: Electrical Characteristics for Microcomputer (IEI-601) The related documents indicated in this publication may include preliminary versions. However, preliminary versions are not marked as such. V805, V810, and V810 Family are trademarks of NEC Corporation. No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document. NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others. While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. NEC devices are classified into the following three quality grades: "Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. The recommended applications of a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device before using it in a particular application. Standard: Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books. If customers intend to use NEC devices for applications other than those specified for Standard quality grade, they should contact an NEC sales representative in advance. Anti-radioactive design is not implemented in this product. M4 96.5 |
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